Special section on the 2001 International Conference on Computer Design (ICCD)

encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCDs unique multidisciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and processor architecture , logic, and circuit design, verification and test methods along with tools and methodologies. ICCD has a proud tradition of bringing together top researchers and developers from academic institutions, research laboratories, and high-technology companies from all over the world. The paper submissions in 2001 came from 18 different countries. Even though the conference was held only days after the shocking and inconceivable events of September 11th, participation was high and by employing remote conferencing, practically no talk had to be cancelled. The great influence of on-chip cache on microprocessor performance becomes evident by the first two papers. The first paper by Heather Hanson et al. " Static energy reduction techniques for microprocessor caches " covers the power dissipation issue. The gain in microprocessor performance by increasing the capacity of on-chip caches comes at the price of increased static energy consumption due to subthreshold leakage currents. This paper compares different techniques for reducing static energy consumption of on-chip level-1 and level-2 caches. One technique employs low-leakage transistors (multithreshold-MTCMOS technique) in the memory cell. Another technique, power-supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. Experiments on the energy/performance tradeoffs of these techniques show that dynamic threshold modulation achieves the best results for level-1 caches, whereas low-leakage transistors perform best for the level-2 cache. The next paper " Address-free memory access based on program syntax correlation of loads and stores " by Lu Peng et al. deals with cache latency which can profoundly impact microprocessor performance in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. The paper describes a new load value speculation mechanism based on the program syntax correlation of stores and loads. Instead of establishing the store/load correlation during runtime, the proposed method establishes a small symbolic cache to capture existing syntax correlations and memory reference locality. The symbolic cache is addressed by …